4. A possible coupling of magnetic field lines, similar to figure 1.

To sum up, the cloth board should follow the following principles:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If leads must be parallel, ensure adequate spacing or use protective wires.

Grounding via

The main problem with RF circuit layout is usually the poor characteristic impedance of the circuit, including the circuit elements and their interconnections. The thin copper coating of the lead is equivalent to the inductance wire and forms distributed capacitance with other neighboring leads. The lead also exhibits inductance and capacitance characteristics as it passes through the hole.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole welding pad and the copper cladding in the stratum, which is separated by a fairly small ring. Another effect comes from the cylinder through the hole itself. The effect of parasitic capacitance is generally small, and usually only causes the edge variation of high-speed digital signals (this is not discussed in this paper).

The biggest effect of over – hole is the parasitic inductance caused by the corresponding interconnection mode. Because in RF PCB design, the size of most metal through hole is the same as that of lumped element, the influence of electric passing hole can be estimated by a simple formula (figure 5) :

Where, LVIA is the lumped inductance through holes; H is the height through the hole, in inches; D is the hole diameter in inches 2. 3. Complete large area grounding helps improve system performance

For an actual inductance, the direction of the lead has great influence on the coupling of magnetic field. If the leads of a sensitive circuit must be close to each other, it is best to align them vertically to reduce coupling (figure 4). If vertical alignment is not possible, consider using guard lines. For protection wire design, please refer to the following grounding and filling treatment section. Numerous applications of industrial, scientific and medical radio frequency (ISM-RF) products show that the PCB layout of these products is prone to various defects. It is often found that the performance index of the same IC installed on two different circuit boards will be significantly different. Changes in working conditions, harmonic radiation, anti-interference capability, start-up time and many other factors can illustrate the importance of circuit board layout in a successful design.

This article lists a variety of design omissions, discusses the causes of each fault and gives advice on how to avoid them. This paper takes a double-layer PCB with a FR-4 dielectric and a thickness of 0.0625in as an example. The operating frequency ranges from 315MHz to 915MHz, and the Tx and Rx power ranges from -120dbm to +13dBm. Table 1 lists some possible PCB layout problems, their causes, and their effects.

Most of these problems stem from a few common causes, which we will discuss one by one.

Inductance direction

When two inductors (or even two PCB wires) are close to each other, mutual inductance is created. The magnetic field generated by the current in the first circuit excites the current in the second circuit (figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the resulting voltage is determined by mutual inductance LM:

Where, YB is the error voltage injected into circuit B, and IA is the current 1 applied to circuit A. LM is very sensitive to circuit spacing, the area of the inductive loop (i.e., magnetic flux), and the direction of the loop. Therefore, the best balance between a compact circuit layout and reduced coupling is to align all inductors in the correct direction.

It can be seen from the magnetic field lines that mutual inductance is related to the direction of inductance arrangement

Adjust the direction of circuit B so that the current loop is parallel to the field lines of circuit A. To achieve this, try to make the inductors perpendicular to each other, refer to the circuit layout of the low-power FSK superheterodyne receiver evaluation (EV) board (MAX7042EVKIT) (figure 2). The circuit board’s three inductors (L3, L1 and L2) are so close together that they are aligned in directions of 0°, 45° and 90°, helping to reduce mutual inductance.

2. As shown in the figure, there are two different PCB layouts. In one layout, the components are arranged in an unreasonable direction (L1 and L3), and the other one is more suitable.

To sum up, the following principles should be followed:

Inductance spacing should be as far as possible.

Inductors are arranged at right angles to minimize crosstalk between inductors.

Lead the coupling

Just as the direction of inductance alignment can affect magnetic coupling, so can leads that are too close to each other. This kind of layout problem can also create what is called mutual sense. One of the most important concerns of RF circuits is the wiring of sensitive components of the system, such as input matching network, resonance channel of receiver, antenna matching network of transmitter, etc.

The return current path should be as close to the main current path as possible to minimize the radiation magnetic field. This layout helps to reduce the current loop area. The ideal low-resistance path for return current is usually the ground area below the lead — effectively limiting the loop area to the area where the dielectric thickness is multiplied by the lead length. However, if the grounding area is divided, the loop area will increase (figure 3). For leads passing through the segmented region, the return current will be forced through the high-resistance path, greatly increasing the current loop area. This layout also makes circuit leads more susceptible to mutual inductance.

5. PCB cross section is used to estimate the through-hole structure of parasitic influence

Parasitic inductors often have a great influence on the connection of bypass capacitors. An ideal by-pass capacitor provides a high-frequency short circuit between the power layer and the formation, but a non-ideal overpass affects the low-sensing path between the formation and the power layer. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Given the specific operating frequency of the ISM-RF product, passing through the hole will adversely affect sensitive circuits (e.g., resonance channel, filter, matching network, etc.).

Other problems arise if sensitive circuits share a through-hole, such as two arms of a PI network. For example, by placing an ideal through-hole equivalent to the lumped inductance, the equivalent principle plan is very different from the original circuit design (FIG. 6). Like crosstalk in a Shared current path 3, leads to increased mutual inductance, increased crosstalk and feed-through.

6. Compared with the ideal architecture and the non-ideal architecture, there are potential “signal paths” in the circuit.

To sum up, circuit layout should follow the following principles:

Be sure to model the through-hole inductance for sensitive areas.

The filter or matching network adopts independent through-hole.

Note that a thinner copper clad PCB reduces the effect of parasitic inductance over the hole.

The length of the lead

Data on Maxim ISM-RF products often recommend the use of the shortest possible high-frequency input and output leads to minimize losses and radiation. On the other hand, this loss is usually caused by non-ideal parasitic parameters, so both parasitic inductors and capacitors affect circuit layout, and using the shortest possible lead helps reduce parasitic parameters. Normally, PCB leads with a width of 10 mil and a distance of 0.0625in from the formation produce inductance of about 19nH/in and distributed capacitance of about 1pF/in if FR4 circuit board is used. For LAN/ mixer circuits with 20nH inductors and 3pF capacitors, very compact circuit and component layout will have a great impact on the effective component value.

The ipc-d-317a4 in the Institute for Printed Circuits provides an industry-standard equation for estimating the various impedance parameters of a microstrip PCB. This file was replaced in 2003 by ipc-2251, which provides more accurate calculation methods for various PCB leads. Online calculators are available from a variety of sources, most of which are based on equations provided by ipc-2251. The electromagnetic compatibility laboratory of Missouri university of technology provides a very practical method for calculating PCB lead impedance 6.

The accepted standard for calculating the impedance of microstrip line is:

Where, the epsilon and loss r is the dielectric constant of the dielectric medium, h is the height of the lead from the formation, w is the width of the lead, and t is the thickness of the lead (FIG. 7). When w/h is between 0.1 and 2.0, and the epsilon epsilon r is between 1 and 15, the formula is quite accurate.

7. This figure shows the PCB cross section (similar to figure 5), representing the structure used to calculate the impedance of the microstrip line.

In order to evaluate the influence of lead length, it is more practical to determine the detuning effect of lead parasitic parameters on ideal circuits. In this example, we discuss stray capacitance and inductance. The standard equation of characteristic capacitance for microstrip line is:

Similarly, the above equation can be used from the equation

The characteristic inductance is calculated as follows:

For example, assume PCB thickness of 0.0625in (h = 62.5 mil), 1 ounce copper-coated lead (t = 1.35 mil), width of 0.01in (w = 10 mil), and fr-4 circuit board. Note that the epsilon and epsilon r of FR-4 is typically 4.35 errand /m per meter (F/m), but ranges from 4.0F/m to 4.7F/m. This example to calculate the characteristic values for Z0 = 134 Ω, C0 = 1.04 m3 / in, L0 = nH / 18.7 in.

For ISM-RF design, the circuit board layout leads with a length of 12.7mm (0.5in) can generate parasitic parameters of about 0.5pF and 9.3nH (figure 8). The influence of parasitic parameters of this level on the resonant channel of the receiver (LC product variation) may result in changes of 315MHz ±2% or 433.92MHz ±3.5%. Due to the additional capacitance and inductance generated by the parasitic effect of leads, the peak value of the 315MHz oscillation frequency reaches 312.17mhz, and the peak value of the 433.92mhz oscillation frequency reaches 426.61mhz.

8. For a compact PCB layout, parasitic effects will affect the circuit.

Another example is the resonance channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pf and 30nH at 315MHz. At 433.92MHz, it is 0pF and 16nH. Calculate resonance circuit oscillation frequency by using equation:

The parasitic effects of packaging and layout should be included in the evaluation of the resonant circuit of the board. When calculating the 315MHz resonant frequency, the parasitic parameters are 7.3pf and 7.5pf respectively. Note that the LC product behaves as a lumped capacitance.

To sum up, cloth board should follow the following principles:

Keep the lead as short as possible.

Key circuits are placed as close to the device as possible.

According to the actual layout parasitic effect to compensate the key components.

A few common reasons 4: grounding and filling handling #e#

Grounding and filling treatment

The ground or power layer defines a common reference voltage that supplies power to all parts of the system through a low-resistance path. Equalizing all electric fields in this way creates a good shielding mechanism.

Direct current always tends to flow along a low resistance path. In the same way, high-frequency current is the path that flows first through the lowest resistance. So, for standard PCB microstrip lines above the ground, the return current tries to flow into the ground area directly below the lead. According to the lead coupling part mentioned above, the cut grounding region will introduce various noises, and then increase crosstalk through magnetic field coupling or current convergence.

9. Keep formation as intact as possible, otherwise return current will cause crosstalk.

The filled ground, also known as a protective line, is often used in designs where it is difficult to lay a continuous ground area in a circuit or where sensitive circuits need to be shielded (figure 10). Increase shielding effect 8 by placing grounding through holes (i.e., through hole arrays) at both ends of the leads or along the lines. Do not mix protection wires with leads designed to provide a return current path. Such a layout introduces crosstalk.

10. Copper clad wire shall be avoided from floating in RF system design, especially when copper skin is needed.

When the coppered area is not grounded (floating) or only grounded at one end, its effectiveness is limited. In some cases, it can cause adverse effects by forming parasitic capacitors, altering the impedance of the surrounding wiring or creating “potential” paths between circuits. In short, if the circuit board is covered with a piece of copper (non-circuit signal wiring) to ensure a consistent plating thickness. The copper-clad areas should be avoided as they may affect the circuit design.

Finally, be sure to consider any grounding area near the antenna. Any unipolar antenna will have the grounding area, wiring and through hole as part of the system balance. Non-ideal balanced wiring will affect the radiation efficiency and direction of the antenna (radiation template). Therefore, the grounding area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Provide continuous, low resistance grounding area as far as possible.

The two ends of the filling line are grounded and the through hole array is adopted as far as possible.

Do not float the copper clad wire near the RF circuit, and do not lay copper skin around the RF circuit.

If the circuit board contains multiple layers, it is best to lay a grounding overhole when the signal line passes from one side to the other.

Crystal capacitance too large

Stray capacitance will cause crystal oscillator operating frequency to deviate from the target value of 9. Therefore, some general guidelines must be followed to reduce stray capacitance in crystal pins, pads, wiring, or connections to RF devices.

The following principles should be followed:

The connection between the crystal and the RF device is as short as possible.

Keep each other’s wiring as isolated as possible.

If the shunt parasitic capacitance is too large, remove the grounding area below the crystal.

Planar wireline inductance

It is not recommended to use planar wiring or PCB spiral inductance. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerance, which greatly affect the precision of component values. Therefore, most controlled and high Q inductors are wound. Second, multilayer ceramic inductors are available, and multilayer chip capacitors are also available. Nevertheless, some designers have chosen spiral inductors as a last resort. The standard formula for calculating planar spiral inductance usually adopts wheeler formula 10:

Where, a is the average radius of the coil in inches; N is the number of turns; C is the width of the coil core (router-rinner), in inches. The accuracy of this method is within 5% when the coil c is less than 0.2a.

Single-layer spiral inductors in square, hexagonal, or other shapes can be used. A very good approximation method can be found to model the planar inductance on IC wafers. In order to achieve this goal, the standard wheeler formula is modified to obtain the plane inductance estimation method 12 which is very suitable for small size and square size.

In the formula, p is the filling ratio:

; N is the number of turns, and dAVG is the average diameter:

. For square spirals, K1 = 2.36, K2 = 2.75. 13

There are many reasons to avoid using such inductors. They are usually spatially limited and result in reduced inductance values. The main reasons for avoiding the use of planar inductors are the limited geometric size and the poor control of the critical size, so the inductance value cannot be predicted. In addition, it is difficult to control actual inductance values during PCB production, and inductance also tends to couple noise to other parts of the circuit (see lead coupling section above).

In a word, it should:

Avoid using flat wire inductors.

Use wound chip inductors whenever possible.

conclusion

As mentioned above, several common PCB layout traps can result